In the field of production of semiconductors, along with higher performance of ultra LSI devices, a finer fabrication technique as an extension of the conventional technique has been reaching the limit of compatibility between higher integration and higher speed. Then, a technique for developing finer semiconductor elements and higher integration in the vertical direction, namely, a technique for multi-layering of a wiring has been developed.
One of the most important techniques in the process of producing devices in which wirings are multi-layered includes a CMP technique. The CMP technique is a technique for forming a thin film on a substrate by chemical vapor deposition (CVD) or the like, subsequently flattening the surface thereof. For example, a flattening treatment by the CMP is essential to ensure a focal depth in lithography. If depressions and projections exist on the surface of the substrate, inconveniences occur, for example, focusing in an exposing step becomes impossible, or a fine wiring structure cannot be sufficiently formed.
In the production process of the device, such a CMP technique is also applied in a step of forming an element separating region by polishing a plasma oxide film (BPSG, HDP-SiO2, p-TEOS), or a step of forming an interlayer dielectric film or a step of embedding a film including silicon oxide in a metal wiring, subsequently flattening a plug (for example, Al—Cu plug).
The CMP is usually performed using an apparatus that can feed a polishing liquid to a polishing pad. The surface of the substrate is polished by pressing the substrate against the polishing pad while the polishing liquid is fed between the surface of the substrate and the polishing pad. Thus, the polishing liquid is one of component technologies in the CMP technique, and development of a variety of polishing liquids has been made in order to obtain a high performance polishing liquid (for example, see Patent Literature 1).
For example, a silicon dioxide film of several tens of thousands Å needs to be polished particularly in the CMP step for the interlayer dielectric film (ILD film) in an interlayer dielectric portion in the semiconductor among the steps in which the CMP technique as described above is applied. For this, in the CMP step for the ILD film, a silica-based polishing liquid having a high polishing rate is mainly used (see Patent Literature 2); in this case, because control of polishing scratches tends to be difficult, the polishing scratches are likely to occur; moreover, usually, mirror finishing polishing is not performed unlike the CMP step for the dielectric film for the element separating region.
However, along with the finer wiring these days, it is desired that the polishing scratch is minimized also in the CMP step for the ILD film. However, the conventional silica-based polishing liquid is difficult to control the polishing scratch as described above. On the other hand, it is known that the amount of polishing scratch is less in the case of the cerium-based polishing liquid than that of the silica-based polishing liquid (see Patent Literature 3), while a high polishing rate required in the CMP step for the ILD film, for example, tends to be difficult to attain.